mere company ki ladkiyaan sunder hain aur lonely hain...
Problem ye hai ki bus voh READ-ONLY hain...
Shayad mere pyar ko taste karna bhool gaye...
Dil sey aisa CUT kiya ke PASTE karna bhool gaye..
Tumhare samne hain itney items kabhi hame bhi pick karo...
Hamare pyar ke ICON pe kabhi to tum DOUBLE-CLICK karo...
Roz subha hum karte hai itne pyar se unhe good morning...
Woh humhe ghoor kar dekhte hain jaise 0 ERRORS but 5 WARNINGS...
Ho gayi galti humse,
Click ho gaya mouse
Duniya ki parwaah chhodo,
Ban jaao meri spouse!
Tumse mila main kal to,
Mere dil mein hua ek sound,
Lekin aaj tum mili
To kehti ho: Your file not found!
Ab aur kaho na tum, "but" ya "if"
Tum ho meri zindagi ki animated gif
Aysa bhi nahin hai ke,
I don't like your face
Par dil ke computer mein,
Nahin hai enough disk space
Ghar se nikalti ho tum jab,
Pehen ke evening gown
Too many requests se,
Ho jaata hai server down
Tumhaare liye pyaar ki application,
Create main karoonga
Tum usse debug karna,
Wait main karoonga
Tumhaara intezaar karte karte,
Main so gaya
Yeh dekho mera connection,
Time out ho gaya
Kya chaal hai tumhaari,
Jaise chalti hai koi cat
What is your ICQ number,
Aao karein chat
Tum jabse meri zindagi mein aayi ho banke female,
Yaad raha na ab kuch na postman na e-mail
Joh sadiyaon se hota aaya hai W
oh repeat kar doonga...
Tu naa mili to tujhko dil sey
Ctrl+Alt+Delete kar doonga...
Humse Kya Khata Hui Ki message Aanna Band Hai.......
Aap hi humse naraz hain ya Web Server band hai.......
Badli hai duniya , kuchch mein bhi badal gaya hoon
Pahle bekaar tha ab S/W Programmer ban gaya hoon
VC aaye to VB mein daal do,
VC aaye to VB mein daal do
seedhe seedhe sabko museebat mein daal do
Project extend ho gaya to kya ho jaata hai?
Are Tankha milti hai aur timepass ho jata hai..
teri yaad me sanam raat bhar humne to wine piya
teri yaad me sanam raat bhar humne to wine piya
kabhi offline to kabhi online piya
Pyar ke sitaare jab gardish mein hote hai
Pyar ke sitaare jab gardish mein hote hai
Laila ghar mein aur majnoo project testing kar rahe hote hai
Tuesday, January 31, 2006
Monday, January 30, 2006
Politically correct statements in a Ph. D thesis
"It has long been known..."
I didn't look up the original reference.
"A definite trend is evident..."
The data is practically useless.
"While it has not been possible to provide definite answers to the questions..."
An unsuccessful experiment, but I still hope to get it published.
"Three of the samples were chosen for detailed study..."
The other results didn't make any sense.
"Typical results are shown..."
This is the prettiest graph.
"These results will be in a subsequent report..."
I might get around to this sometime, if pushed/funded.
"The most reliable results are obtained by xxxxx..."
Xxxxx was my graduate student; his grade depended on this.
"In my experience..."
Once.
"In case after case..."
Twice.
"In a series of cases..."
Thrice.
"It is believed that..."
I think.
"It is generally believed that..."
A couple of other guys think so too.
"Correct within an order of magnitude..."
Wrong.
"According to the statistical analysis..."
Rumor has it.
"A statistically oriented projection of the significance of these findings..."
A wild guess.
"A careful analysis of obtainable data..."
Three pages of notes were obliterated when I knocked over a glass of beer.
"It is clear that much additional work will be required before a complete understanding of this phenomena occurs..."
I don't understand it.
"After additional study by my colleagues..."
They don't understand it either.
"Thanks are due to Mr. Smith for assisstance with the experiment and Miss Jones for valuable discussions..."
Harry Smith did the experiment and Mary Jones explained to me what it meant.
"A highly significant area for exploratory study..."
A totally useless topic selected by my committee.
"It is hoped that this study will stimulate further investigation in this field..."
I quit.
I didn't look up the original reference.
"A definite trend is evident..."
The data is practically useless.
"While it has not been possible to provide definite answers to the questions..."
An unsuccessful experiment, but I still hope to get it published.
"Three of the samples were chosen for detailed study..."
The other results didn't make any sense.
"Typical results are shown..."
This is the prettiest graph.
"These results will be in a subsequent report..."
I might get around to this sometime, if pushed/funded.
"The most reliable results are obtained by xxxxx..."
Xxxxx was my graduate student; his grade depended on this.
"In my experience..."
Once.
"In case after case..."
Twice.
"In a series of cases..."
Thrice.
"It is believed that..."
I think.
"It is generally believed that..."
A couple of other guys think so too.
"Correct within an order of magnitude..."
Wrong.
"According to the statistical analysis..."
Rumor has it.
"A statistically oriented projection of the significance of these findings..."
A wild guess.
"A careful analysis of obtainable data..."
Three pages of notes were obliterated when I knocked over a glass of beer.
"It is clear that much additional work will be required before a complete understanding of this phenomena occurs..."
I don't understand it.
"After additional study by my colleagues..."
They don't understand it either.
"Thanks are due to Mr. Smith for assisstance with the experiment and Miss Jones for valuable discussions..."
Harry Smith did the experiment and Mary Jones explained to me what it meant.
"A highly significant area for exploratory study..."
A totally useless topic selected by my committee.
"It is hoped that this study will stimulate further investigation in this field..."
I quit.
Saturday, January 28, 2006
Processor Pipeline
This is probably one of the most confusing parts of the processor to understand. The processor pipeline is like a conveyor belt. Now, imagine that instructions for the processor to carry out is food. The way a pipeline works is like this: the food moves along the conveyor belt, and when it gets to the other end of the conveyor belt that instruction is done. That is the simple way, but that is not technically correct. The way it works is this, (can’t think of any other way to explain it here) an instruction is fetched from the cache, then it continues to a different part of the pipeline, and so on. There are lots of different pipeline sizes, it all depends on what processor you have. This will explain how AMD manages to perform against Intel, even though Intel has a much higher clock speed than AMD.
The different parts of the pipeline perform different jobs. Some parts of the pipeline are duplicated, and adds to the length of the pipeline. Also, there can be more than one pipeline, which is why modern processors are said to have a super scalar architecture. The reason parts of the pipeline are duplicated is so less work has to be done at each stage. This means more instructions are completed in the same amount of time, speeding up performance. This is one of the key reasons AMD is able to contend with Intel. AMD Athlon XP’s have 3 X86 decoders, 3 floating-point pipelines, and 3 integer pipelines. This is compared with Intel’s Pentium 4, which has only one X86 decoder, 2 floating-point pipelines, and 1 more integer pipeline than AMD’s Athlon. This leads to AMD being able to decode more instructions than Intel at the same time, and being able to perform floating-point operations quicker than Intel. Overall, AMD Athlon XP processors are able to perform 9 operations per clock cycle while Intel can only manage 6. It doesn’t sound like much, but in processors every operation is crucial. This is why I said AMD are more about getting more done per clock cycle in my AMD processor buying guide.
This doesn’t mean it’s all over for Intel though. Even though AMD manages to perform more operations than Intel in one clock cycle, Intel manages to do their operations quicker. This is because of their pipeline architecture. AMD’s pipeline is only 10 stages long. This means that because the stages in the pipeline have to do more work, they can’t run very fast. Now, with Intel, their processors have a 20 stage pipeline (Prescott core processors have 31 stages). This means that the processor can run at a higher clock speed, because less work is done in each stage of the pipeline. The reason the Prescott core has been released is because this brings yet more speed. Because there are 31 stages, even less work is done, which means even higher clock speeds.
This can be linked to CISC computing and RISC computing. CISC stands for complex instruction set computing, and RISC stands for reduced instruction set computing. RISC means having less complex instructions for the processor. Here is an example of CISC giving someone commands. With CISC it would look like this:
1. Get food
2. Get fork
3. Eat
But with RISC it would be like this:
1. Go to kitchen
2. open fridge
3. get food
4. close fridge
5. open drawer
6. get fork
7. close drawer
8. open mouth
9. put food in mouth
10. close mouth
11. chew
12. swallow
The reason the CISC is more complex is because the processor has a lot more to do in one instruction. RISC is more efficient because it is very simple instructions, meaning less "thinking" is needed to perform the instruction, resulting in faster speed. Also, using RISC means there is less transistors needed in a processor, reducing cost. This is why all modern processors are RISC processors. But there is something you should know about X86 (the way the instructions are coded). X86 is actually built using a CISC architecture. This is why the processors need X86 decoders, to convert the CISC instructions into RISC instructions.
Now, even though Intel has the advantage of faster clock speeds, this doesn’t work well unless you have a lot of something. Cache. Cache is where all the instructions the processor is going to work on resides. All the cache’s data comes from main memory (RAM). When a processor is going to work on an instruction, it checks the cache to see if it is there. Cache runs at the core speed of the processor, so if you have an Intel 2.6GHz processor, the cache will also be running at 2.6GHz. Now compare this to main memory. Main memory, at the most without over clocking, runs at 400MHz. If a processor can’t find an instruction in the cache, then it has to slow right down to match the speed of the main memory, until it can get the next instruction from it. This makes a massive drop in performance, and is the reason the Celeron processors are such poor performers. With less cache, there are fewer instructions ready for the processor, increasing the chance that the processor will have to slow down to main memory speed. The reason the Intel processors are more susceptible to slowing down is because of a technique processors use to decide which instruction to work on next.
This is what is called pipeline optimization: The processor will always try to keep the pipeline full. To do this, it has to use techniques to guess what will come next. There are 3 different ways of optimizing the pipeline. These ways are:
Speculative execution - This is where the CPU has an instruction, and the next instruction cannot take place unless the CPU knows the answer to the first instruction. The CPU has to work out the answer to the first instruction, but say there is 2 instruction answers, and only one is correct. Without speculative execution, the CPU would send one of the possible answers to the instruction down the pipeline, which in an Intel CPU would take 20 clock cycles to complete. Now, if the CPU chooses the correct instruction answer, then everything is fine, the CPU can go right onto the next one. But what if it is the wrong one? The CPU has to send the other instruction answer down the pipeline, which would mean 20 clock cycles were wasted with the first instruction! So what speculative execution does is send both possible instruction answers down the pipeline, so the CPU processes both. The CPU processes both, then discards the incorrect one. That means a lot less time was wasted.
Branch prediction - This is a tough one, and can mean running at full speed without having to slow down, or having to completely start again from the start of the instruction set for a processor. This builds onto speculative execution. Remember when I said the processor will always want a full pipeline? Well, just because there is 2 possible answers doesn’t mean there is any exception. What will happen is this: The processor will see the 2 possible answers, and will make an educated guess which one is correct from the branch target buffer before the CPU executes both instructions. So, both instructions are not executed anymore, only one of them is, which is the one the CPU predicts will be correct. The branch target buffer is a bank of all the answers that turned out to be right from other instructions, and from looking at this bank the CPU can take a guess which is the correct answer from what it has already done. When the CPU looks in this bank, it allows a good prediction because it has all the results from other instructions. So after sending the instruction that the CPU has guessed correct, the instructions that would come after this prediction are also sent down the pipeline. If the CPU was right with the branch prediction, then there will be a lot of time saved. If not, the whole pipeline has to be flushed and restarted, because it all counted on the first instruction being guessed correctly. This is why the Pentium 4 needs more intelligent branch prediction technology, with a long pipeline it takes a long time for a new set of instructions to reach the end of the pipeline.
Out of order execution - This is where the second instruction cannot be performed, because the CPU has to know the answer to the first instruction before the CPU can know what the answer is to the second one. Without out of order execution, the CPU would execute the first instruction, and leave the rest of the pipeline empty. This would be a massive waste of resources. So what happens is this, the CPU will execute the first instruction, then execute other instructions that have no dependency on the first instruction. So with this, the CPU can work on other instructions while it is waiting for the first one.
The different parts of the pipeline perform different jobs. Some parts of the pipeline are duplicated, and adds to the length of the pipeline. Also, there can be more than one pipeline, which is why modern processors are said to have a super scalar architecture. The reason parts of the pipeline are duplicated is so less work has to be done at each stage. This means more instructions are completed in the same amount of time, speeding up performance. This is one of the key reasons AMD is able to contend with Intel. AMD Athlon XP’s have 3 X86 decoders, 3 floating-point pipelines, and 3 integer pipelines. This is compared with Intel’s Pentium 4, which has only one X86 decoder, 2 floating-point pipelines, and 1 more integer pipeline than AMD’s Athlon. This leads to AMD being able to decode more instructions than Intel at the same time, and being able to perform floating-point operations quicker than Intel. Overall, AMD Athlon XP processors are able to perform 9 operations per clock cycle while Intel can only manage 6. It doesn’t sound like much, but in processors every operation is crucial. This is why I said AMD are more about getting more done per clock cycle in my AMD processor buying guide.
This doesn’t mean it’s all over for Intel though. Even though AMD manages to perform more operations than Intel in one clock cycle, Intel manages to do their operations quicker. This is because of their pipeline architecture. AMD’s pipeline is only 10 stages long. This means that because the stages in the pipeline have to do more work, they can’t run very fast. Now, with Intel, their processors have a 20 stage pipeline (Prescott core processors have 31 stages). This means that the processor can run at a higher clock speed, because less work is done in each stage of the pipeline. The reason the Prescott core has been released is because this brings yet more speed. Because there are 31 stages, even less work is done, which means even higher clock speeds.
This can be linked to CISC computing and RISC computing. CISC stands for complex instruction set computing, and RISC stands for reduced instruction set computing. RISC means having less complex instructions for the processor. Here is an example of CISC giving someone commands. With CISC it would look like this:
1. Get food
2. Get fork
3. Eat
But with RISC it would be like this:
1. Go to kitchen
2. open fridge
3. get food
4. close fridge
5. open drawer
6. get fork
7. close drawer
8. open mouth
9. put food in mouth
10. close mouth
11. chew
12. swallow
The reason the CISC is more complex is because the processor has a lot more to do in one instruction. RISC is more efficient because it is very simple instructions, meaning less "thinking" is needed to perform the instruction, resulting in faster speed. Also, using RISC means there is less transistors needed in a processor, reducing cost. This is why all modern processors are RISC processors. But there is something you should know about X86 (the way the instructions are coded). X86 is actually built using a CISC architecture. This is why the processors need X86 decoders, to convert the CISC instructions into RISC instructions.
Now, even though Intel has the advantage of faster clock speeds, this doesn’t work well unless you have a lot of something. Cache. Cache is where all the instructions the processor is going to work on resides. All the cache’s data comes from main memory (RAM). When a processor is going to work on an instruction, it checks the cache to see if it is there. Cache runs at the core speed of the processor, so if you have an Intel 2.6GHz processor, the cache will also be running at 2.6GHz. Now compare this to main memory. Main memory, at the most without over clocking, runs at 400MHz. If a processor can’t find an instruction in the cache, then it has to slow right down to match the speed of the main memory, until it can get the next instruction from it. This makes a massive drop in performance, and is the reason the Celeron processors are such poor performers. With less cache, there are fewer instructions ready for the processor, increasing the chance that the processor will have to slow down to main memory speed. The reason the Intel processors are more susceptible to slowing down is because of a technique processors use to decide which instruction to work on next.
This is what is called pipeline optimization: The processor will always try to keep the pipeline full. To do this, it has to use techniques to guess what will come next. There are 3 different ways of optimizing the pipeline. These ways are:
Speculative execution - This is where the CPU has an instruction, and the next instruction cannot take place unless the CPU knows the answer to the first instruction. The CPU has to work out the answer to the first instruction, but say there is 2 instruction answers, and only one is correct. Without speculative execution, the CPU would send one of the possible answers to the instruction down the pipeline, which in an Intel CPU would take 20 clock cycles to complete. Now, if the CPU chooses the correct instruction answer, then everything is fine, the CPU can go right onto the next one. But what if it is the wrong one? The CPU has to send the other instruction answer down the pipeline, which would mean 20 clock cycles were wasted with the first instruction! So what speculative execution does is send both possible instruction answers down the pipeline, so the CPU processes both. The CPU processes both, then discards the incorrect one. That means a lot less time was wasted.
Branch prediction - This is a tough one, and can mean running at full speed without having to slow down, or having to completely start again from the start of the instruction set for a processor. This builds onto speculative execution. Remember when I said the processor will always want a full pipeline? Well, just because there is 2 possible answers doesn’t mean there is any exception. What will happen is this: The processor will see the 2 possible answers, and will make an educated guess which one is correct from the branch target buffer before the CPU executes both instructions. So, both instructions are not executed anymore, only one of them is, which is the one the CPU predicts will be correct. The branch target buffer is a bank of all the answers that turned out to be right from other instructions, and from looking at this bank the CPU can take a guess which is the correct answer from what it has already done. When the CPU looks in this bank, it allows a good prediction because it has all the results from other instructions. So after sending the instruction that the CPU has guessed correct, the instructions that would come after this prediction are also sent down the pipeline. If the CPU was right with the branch prediction, then there will be a lot of time saved. If not, the whole pipeline has to be flushed and restarted, because it all counted on the first instruction being guessed correctly. This is why the Pentium 4 needs more intelligent branch prediction technology, with a long pipeline it takes a long time for a new set of instructions to reach the end of the pipeline.
Out of order execution - This is where the second instruction cannot be performed, because the CPU has to know the answer to the first instruction before the CPU can know what the answer is to the second one. Without out of order execution, the CPU would execute the first instruction, and leave the rest of the pipeline empty. This would be a massive waste of resources. So what happens is this, the CPU will execute the first instruction, then execute other instructions that have no dependency on the first instruction. So with this, the CPU can work on other instructions while it is waiting for the first one.
Thursday, January 19, 2006
Indian Air Force finally apologizes to Mrs. Kavita Gadgil
The results of an internet search by the grieving mother of a MIG-21 pilot killed in a 2001 crash forced the IAF to finally admit that the young officer was not responsible for his own death.
Four years—and endless letters, emails and phone calls—after Flt Lt Abhijeet Gadgil died in a fiery crash, Kavita Gadgil (54) just got some kind of closure in the form of an apology from Air Chief Marshal S P Tyagi.
Until now, the IAF said it shared Gadgil’s anguish but implied that a lack of flying skills claimed the life of Lt Gadgil in Rajasthan on September 17, 2001.
Worse, on behalf of the IAF, Air Marshal Ashok Goel wrote to Gadgil in March 2003, accusing her of carrying a ‘‘public tirade’’ which would ‘‘demoralise the force and would not be in the best interest of the nation’’.
But on March 23 this year—five days after an Air Marshal was flown to Mumbai from air headquarters in Delhi to apologise—Air Chief Marshal S P Tyagi finally acknowledged in a letter to Gadgil that her son’s crash ‘‘may have been triggered by a trim malfunction’’. Tyagi also said the IAF was expunging Goel’s letter from its records.
In the end, the door Gadgil was looking for came from an internet search on spatial disorientation: it put her in touch with an IAF doctor on the panel of the crash inquiry.
A case study published by aviation medicine specialist, Wing Cdr (Dr) R Ravi in the Indian Journal of Aerospace Medicine quoted details of the crash, without naming the pilot: it was apparent pilot error was not the cause.
Armed with this evidence, Gadgil approached the air chief. Last week, the Air Marshal flew down to meet her.
‘‘But I wanted nothing less than an admission from the Chief,’’ said Gadgil, whose husband, a 20-year veteran of the IAF pilot, is about to retire from Air-India.
That admission came in the letter to the Gadgils: Tyagi expressed his condolences and regret.
‘‘He (Lt Gadgil) was a good member of the IAF, and his loss would be difficult to replace,’’ wrote the chief.
The apology is unprecedented, but for Gadgil it comes late.
‘‘How many Kavita Gadgils will have to stand up to be counted? Is it worth it?’’ asked Gadgil, whose determined, unwavering campaign against the MIG-21—157 pilots have died in more than 360 crashes since the 1970s—has taken her to President A P J Abdul Kalam.
‘‘I have put aside my pain all these years to reach the truth,’’ Gadgil said.
In February 2003, Gadgil first wrote to the Chief of Air Staff, asking why Abhijeet’s plane crashed. She was told the accident resulted from the pilot’s ‘‘spatial disorientation’’.
A spate of letters—the last in August 2004—and e-mails had no result. It was after she approached the National Human Rights Commision (NHRC) in December that the air chief wrote.
Gadgil said she is a staunch supporter of the IAF.
‘‘You can buy F16s, but you can’t buy the pilots,’’ she said. ‘‘We have such fine boys joining the force. So many more Abhijeets are still flying. But we need some transperancy. The Air Force has taught me many things. But we also have a right to ask the IAF: ‘what are you doing with our sons?’’
Four years—and endless letters, emails and phone calls—after Flt Lt Abhijeet Gadgil died in a fiery crash, Kavita Gadgil (54) just got some kind of closure in the form of an apology from Air Chief Marshal S P Tyagi.
Until now, the IAF said it shared Gadgil’s anguish but implied that a lack of flying skills claimed the life of Lt Gadgil in Rajasthan on September 17, 2001.
Worse, on behalf of the IAF, Air Marshal Ashok Goel wrote to Gadgil in March 2003, accusing her of carrying a ‘‘public tirade’’ which would ‘‘demoralise the force and would not be in the best interest of the nation’’.
But on March 23 this year—five days after an Air Marshal was flown to Mumbai from air headquarters in Delhi to apologise—Air Chief Marshal S P Tyagi finally acknowledged in a letter to Gadgil that her son’s crash ‘‘may have been triggered by a trim malfunction’’. Tyagi also said the IAF was expunging Goel’s letter from its records.
In the end, the door Gadgil was looking for came from an internet search on spatial disorientation: it put her in touch with an IAF doctor on the panel of the crash inquiry.
A case study published by aviation medicine specialist, Wing Cdr (Dr) R Ravi in the Indian Journal of Aerospace Medicine quoted details of the crash, without naming the pilot: it was apparent pilot error was not the cause.
Armed with this evidence, Gadgil approached the air chief. Last week, the Air Marshal flew down to meet her.
‘‘But I wanted nothing less than an admission from the Chief,’’ said Gadgil, whose husband, a 20-year veteran of the IAF pilot, is about to retire from Air-India.
That admission came in the letter to the Gadgils: Tyagi expressed his condolences and regret.
‘‘He (Lt Gadgil) was a good member of the IAF, and his loss would be difficult to replace,’’ wrote the chief.
The apology is unprecedented, but for Gadgil it comes late.
‘‘How many Kavita Gadgils will have to stand up to be counted? Is it worth it?’’ asked Gadgil, whose determined, unwavering campaign against the MIG-21—157 pilots have died in more than 360 crashes since the 1970s—has taken her to President A P J Abdul Kalam.
‘‘I have put aside my pain all these years to reach the truth,’’ Gadgil said.
In February 2003, Gadgil first wrote to the Chief of Air Staff, asking why Abhijeet’s plane crashed. She was told the accident resulted from the pilot’s ‘‘spatial disorientation’’.
A spate of letters—the last in August 2004—and e-mails had no result. It was after she approached the National Human Rights Commision (NHRC) in December that the air chief wrote.
Gadgil said she is a staunch supporter of the IAF.
‘‘You can buy F16s, but you can’t buy the pilots,’’ she said. ‘‘We have such fine boys joining the force. So many more Abhijeets are still flying. But we need some transperancy. The Air Force has taught me many things. But we also have a right to ask the IAF: ‘what are you doing with our sons?’’
Thursday, January 05, 2006
Largest prime number discovered...
This article was of interest since I had studied Mersenne primes (2^p - 1, where p is a prime number) in Cryptology class. However, the p that I used was almost always unary.....
The team at Central Missouri State University, led by associate dean Steven Boone and mathematics professor Curtis Cooper, found it in mid-December after programming 700 computers years ago.
A prime number is a positive number divisible by only itself and 1 -- 2, 3, 5, 7 and so on.
The number that the team found is 9.1 million digits long. It is a Mersenne prime known as M30402457 -- that's 2 to the 30,402,457th power minus 1.
Mersenne primes are a special category expressed as 2 to the "p" power minus 1, in which "p" also is a prime number.
"We're super excited," said Boone, a chemistry professor. "We've been looking for such a number for a long time."
The discovery is affiliated with the Great Internet Mersenne Prime Search, a global contest using volunteers who run software that searches for the largest Mersenne prime.
The team at Central Missouri State University, led by associate dean Steven Boone and mathematics professor Curtis Cooper, found it in mid-December after programming 700 computers years ago.
A prime number is a positive number divisible by only itself and 1 -- 2, 3, 5, 7 and so on.
The number that the team found is 9.1 million digits long. It is a Mersenne prime known as M30402457 -- that's 2 to the 30,402,457th power minus 1.
Mersenne primes are a special category expressed as 2 to the "p" power minus 1, in which "p" also is a prime number.
"We're super excited," said Boone, a chemistry professor. "We've been looking for such a number for a long time."
The discovery is affiliated with the Great Internet Mersenne Prime Search, a global contest using volunteers who run software that searches for the largest Mersenne prime.
Wednesday, January 04, 2006
What happens in Vegas.....stays in Vegas
A California couple left their 5- and 9-year-old children home alone for the weekend while they went to gamble in Las Vegas.
Police said the parents could be charged with child neglect but have not been able to interview the couple in person because bad weather was delaying their return from Las Vegas until Wednesday.
The couple went to Las Vegas on Friday, leaving the children cereal to eat and the father's cell phone number to call in an emergency.
Their apparent hope that, in the words of the city's tourism advertisements, what happens in Las Vegas should stay in Las Vegas went awry when one of their mothers called their home on New Year's Eve and became concerned that no adult was present, said Brian Kilinowski, investigation supervisor for the San Ramon police south of San Francisco.
The children, who ate cereal for breakfast and frozen foods heated in a microwave for other meals, were unharmed.
Police said the parents could be charged with child neglect but have not been able to interview the couple in person because bad weather was delaying their return from Las Vegas until Wednesday.
The couple went to Las Vegas on Friday, leaving the children cereal to eat and the father's cell phone number to call in an emergency.
Their apparent hope that, in the words of the city's tourism advertisements, what happens in Las Vegas should stay in Las Vegas went awry when one of their mothers called their home on New Year's Eve and became concerned that no adult was present, said Brian Kilinowski, investigation supervisor for the San Ramon police south of San Francisco.
The children, who ate cereal for breakfast and frozen foods heated in a microwave for other meals, were unharmed.
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